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Proceedings Paper

Sampling plan optimization for CD control in low k1 lithography
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Paper Abstract

For advanced process control, a sampling plan for critical dimension measurement is optimized through empirical considerations concerning the nature of error and a statistical approach. The metric of the optimization is the accuracy of lot mean estimation. In this work, critical dimension errors are classified into static and dynamic components. The static component is defined as the error which repeats through lots while keeping its tendency, and the dynamic as the error whose tendency changes by lot. In the basic concept of our sampling plan, sampling positions and size are determined from the static and dynamic error, respectively. The balance of sampling number of wafer, field and pattern is obtained under the restriction of total sampling size by a statistical theory with some assumptions. Based on the concept, we could make a sampling plan for 65 nm CMOS lithography.

Paper Details

Date Published: 10 May 2005
PDF: 9 pages
Proc. SPIE 5752, Metrology, Inspection, and Process Control for Microlithography XIX, (10 May 2005); doi: 10.1117/12.600370
Show Author Affiliations
Masafumi Asano, Semiconductor Co., Toshiba Corp. (Japan)
Toru Koike, Semiconductor Co., Toshiba Corp. (Japan)
Toru Mikami, Semiconductor Co., Toshiba Corp. (Japan)
Hideaki Abe, Semiconductor Co., Toshiba Corp. (Japan)
Takahiro Ikeda, Semiconductor Co., Toshiba Corp. (Japan)
Satoshi Tanaka, Semiconductor Co., Toshiba Corp. (Japan)
Shoji Mimotogi, Semiconductor Co., Toshiba Corp. (Japan)


Published in SPIE Proceedings Vol. 5752:
Metrology, Inspection, and Process Control for Microlithography XIX
Richard M. Silver, Editor(s)

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