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Proceedings Paper

A novel design-process optimization technique based on self-consistent electrical performance evaluation
Author(s): Valery Axelrad; Andrei Shibkov; Gene Hill; Hung-Jen Lin; Cyrus Tabery; Dan White; Victor Boksha; Randy Thilmany
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Paper Abstract

Accurate manufacturing of devices at sub-wavelength nodes is becoming increasingly difficult. Lithography and lithographic process effects are quickly becoming a major concern for physical designers working at sub-wavelength process nodes. Beyond the rapidly expanding design rule deck, physical designers must have deeper access to and understanding of the process in order to grasp the full impact of layout changes on electrical performance. Process aberrations, such as misalignment, are manifested as CD variation resulting in parametric shifts and systematic yield problems. These yield issues must be addressed by designers, but designers do not have adequate tools nor information to fully comprehend these issues. To correct this situation, a new approach is needed to bring information from the manufacturing process upstream into the design creation process. This work extends and generalizes concepts presented in [1-3] and presents an integrated implementation of the methodology in a complete, self-consistent flow. This methodology integrates calibrated process simulation, electrical circuit performance analysis and optionally, automatic Optical Proximity Correction (OPC) into a comprehensive Design-for-Manufacturing (DFM) flow. Process window simulations uncover design-process interactions across multiple process variables (misalignment, bias, etc.). To characterize the process, a design of experiments qualifies the impact of design variation on electrical performance. Data from these experiments is used to refine and calibrate process simulation models, ensuring accurate simulation. As a result, this procedure identifies critical performance and systematic yield issues prior to tapeout, eliminating costly design respins and preserving design intent.

Paper Details

Date Published: 5 May 2005
PDF: 8 pages
Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005); doi: 10.1117/12.600283
Show Author Affiliations
Valery Axelrad, Sequoia Design Systems, Inc. (United States)
Andrei Shibkov, Sequoia Design Systems, Inc. (United States)
Gene Hill, AMD/Spansion (United States)
Hung-Jen Lin, AMD/Spansion (United States)
Cyrus Tabery, AMD/Spansion (United States)
Dan White, HPL Technologies, Inc. (United States)
Victor Boksha, HPL Technologies, Inc. (United States)
Randy Thilmany, HPL Technologies, Inc. (United States)

Published in SPIE Proceedings Vol. 5756:
Design and Process Integration for Microelectronic Manufacturing III
Lars W. Liebmann, Editor(s)

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