Share Email Print
cover

Proceedings Paper

Building an infrastructure for parametric yield analysis: concept and implementation of a DFM platform
Author(s): John Gookassian; Bob Pack; Mitch Heins; John Garcia; Hitendra Divecha; Brian Gordon; Dean Frazier; Dan White; Gurgen Lachinyan; Brian Dillon; Christophe Suzor; Anthony Adamov; Kyung-Youl Min; Sergei Bakarian; Rafik Marutyan; Victor Boksha
Format Member Price Non-Member Price
PDF $17.00 $21.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

There is a growing realization of the need for highly integrated solutions enabled by new bi-directional data 'pipes' between design and manufacturing. Traditional EDA applications should be able to communicate and collaborate with yield analysis software. Simply adding such capabilities to existing EDA applications is not feasible. Thus, there is a need for an infrastructure that would enable such interaction in a standard way. We call this infrastructure the DFM Platform. In this article we present new approach to building such a platform. Brief descriptions of potential applications follow the platform architecture. "Via analysis" application includes test chips capabilities, critical area and critical parameter analysis to predict yield for a real design. The "DFM Cell Grading" module applies the concept of DFM to IP Libraries.

Paper Details

Date Published: 5 May 2005
PDF: 11 pages
Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005); doi: 10.1117/12.600261
Show Author Affiliations
John Gookassian, HPL Technologies, Inc. (United States)
Bob Pack, HPL Technologies, Inc. (United States)
Mitch Heins, HPL Technologies, Inc. (United States)
John Garcia, HPL Technologies, Inc. (United States)
Hitendra Divecha, HPL Technologies, Inc. (United States)
Brian Gordon, HPL Technologies, Inc. (United States)
Dean Frazier, HPL Technologies, Inc. (United States)
Dan White, HPL Technologies, Inc. (United States)
Gurgen Lachinyan, HPL Technologies, Inc. (United States)
Brian Dillon, HPL Technologies, Inc. (United States)
Christophe Suzor, HPL Technologies, Inc. (United States)
Anthony Adamov, HPL Technologies, Inc. (United States)
Kyung-Youl Min, HPL Technologies, Inc. (United States)
Sergei Bakarian, HPL Technologies, Inc. (United States)
Rafik Marutyan, HPL Technologies, Inc. (United States)
Victor Boksha, HPL Technologies, Inc. (United States)


Published in SPIE Proceedings Vol. 5756:
Design and Process Integration for Microelectronic Manufacturing III
Lars W. Liebmann, Editor(s)

© SPIE. Terms of Use
Back to Top