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Proceedings Paper

New OPC methods to increase process margin for sub-70nm devices
Author(s): Ji-Suk Hong; Dong-Hyun Kim; Sang-Wook Kim; Moon-Hyun Yoo; Jeong-Taek Kong
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Paper Abstract

Current model-based OPC methods are targeting the critical dimension and the fidelity of the design layout. These methods cannot suitably consider the process margin and reveal several problems below 70nm design layout with the low k1 process factor. Although litho-friendly layout methods have been introduced to improve the photolithography process margin, designing perfect litho-friendly layout is difficult because of the designer’s lacking of knowledge about the process and the relationship between the layers. Thus we have developed new OPC methods to increase the process margin for sub-70nm process. In this paper we propose new methods to generate the OPC-friendly layout from the original design by 1) rule-based retargeting, 2) model-based retargeting using NILS values, and 3) model-based retargeting by MEEF values. In addition, we have evaluated the post-processing treatment by NILS or MEEF values after the model-based OPC. The proposed OPC methods are effective for the memory bit line layer and metal layers, which are composed of the complicated 2-dimensional configuration and also have the advantage to compensate the model inaccuracy for the layout having non-periodic pattern structure. While the rule-based retargeting method requires high engineering cost to optimize the retargeting rule, the model-based retargeting method can be easily implemented into the conventional OPC process and do not need the extraction process of the retargeting rule which is not simple for the 2-dimensional patterns. Applying the model-based retargeting we could increase the DOF margin by 50% compared to the normal OPC method for sub-70nm memory device with ArF lithography. It is more effective to use these retargeting methods from the defocused OPC models.

Paper Details

Date Published: 5 May 2005
PDF: 11 pages
Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005); doi: 10.1117/12.600231
Show Author Affiliations
Ji-Suk Hong, SAMSUNG Electronics Co., Ltd. (South Korea)
Dong-Hyun Kim, SAMSUNG Electronics Co., Ltd. (South Korea)
Sang-Wook Kim, SAMSUNG Electronics Co., Ltd. (South Korea)
Moon-Hyun Yoo, SAMSUNG Electronics Co., Ltd. (South Korea)
Jeong-Taek Kong, SAMSUNG Electronics Co., Ltd. (South Korea)

Published in SPIE Proceedings Vol. 5756:
Design and Process Integration for Microelectronic Manufacturing III
Lars W. Liebmann, Editor(s)

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