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Proceedings Paper

Post-CMOS chip-level processing for high-aspect-ratio microprobe fabrication utilizing pulse plating
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Paper Abstract

A post-CMOS process for chip-level monolithic integration has been developed. A metal probe array for recording neural signals is utilized as a test vehicle to realize the integration process. This probe array is fabricated on a 2 mm x 2 mm chip containing eight ultra-low power CMOS operational amplifiers. A LIGA-like process is employed utilizing UV lithography on SU-8 photoresist and pulse electroplating technique. Pulse plating significantly reduces stress in the deposited material. The post-CMOS fabrication process is utilized to fabricate 70 μm high probes having different aspect-ratios that are monolithically integrated on the CMOS chip.

Paper Details

Date Published: 16 May 2005
PDF: 10 pages
Proc. SPIE 5763, Smart Structures and Materials 2005: Smart Electronics, MEMS, BioMEMS, and Nanotechnology, (16 May 2005); doi: 10.1117/12.600128
Show Author Affiliations
Tinghui Xin, Louisiana State Univ. (United States)
Pratul K. Ajmera, Louisiana State Univ. (United States)
Chuang Zhang, Louisiana State Univ. (United States)
Ashok Srivastava, Louisiana State Univ. (United States)

Published in SPIE Proceedings Vol. 5763:
Smart Structures and Materials 2005: Smart Electronics, MEMS, BioMEMS, and Nanotechnology
Vijay K. Varadan, Editor(s)

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