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Proceedings Paper

A novel contact hole shrink process for the 65-nm-node and beyond
Author(s): Richard Peters; Patrick Montgomery; Cesar Garza; Stanley Filipiak; Tab Stephens; Dan Babbitt
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Paper Abstract

Patterning of sub-100nm contacts for sub-90-nm-node devices is one of the primary challenges of photolithography today. The challenge involves achieving the desired resolution while maintaining manufacturable process windows. Increases in numerical aperture and reductions in target CDs will continue to shrink process windows and increase mask error factor resulting in larger CD variation. Several techniques such as RELACS, SAFIER, and resist reflow have been developed to improve the resolution of darkfield patterns such as contacts and trenches. These techniques are all post-develop processes applied to the patterned resist. Reflow is a fast process with low cost of ownership, but has two major disadvantages of high temperature sensitivity and large proximity bias. SAFIER and RELACS both have much slower throughput and higher cost of ownership than reflow. SAFIER also is sensitive to temperature and has large proximity bias. In this paper, a novel process is described that reduces the diameter of contact holes in resist up to 25nm without proximity effects. This process uniformly swells the resist film resulting in a shrink of patterned holes or trenches. Results are shown for 248nm and 193nm single layer resists, and a 193nm bilayer resist. This process has the potential to be high throughput with low cost of ownership similar to reflow techniques but without the proximity effects and thermal sensitivity observed with reflow.

Paper Details

Date Published: 4 May 2005
PDF: 11 pages
Proc. SPIE 5753, Advances in Resist Technology and Processing XXII, (4 May 2005); doi: 10.1117/12.599918
Show Author Affiliations
Richard Peters, Freescale Semiconductor Technology Solutions Organisation (United States)
Patrick Montgomery, Freescale Semiconductor Technology Solutions Organisation (United States)
Cesar Garza, Freescale Semiconductor, Inc. (United States)
Stanley Filipiak, Freescale Semiconductor, Inc. (United States)
Tab Stephens, Freescale Semiconductor, Inc. (United States)
Dan Babbitt, Freescale Semiconductor, Inc. (United States)


Published in SPIE Proceedings Vol. 5753:
Advances in Resist Technology and Processing XXII
John L. Sturtevant, Editor(s)

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