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Proceedings Paper

OPC accuracy enhancement through systematic OPC calibration and verification methodology for sub-100nm node
Author(s): Hyunjo Yang; Jaeseung Choi; Byungug Cho; Byeongho Cho; Donggyu Yim; Jinwoong Kim
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Paper Abstract

New generation DRAM devices such as high speed Graphic DRAMs demand smaller size transistors and very precise CD control. However, the application of very high NA and aggressive Resolution Enhancement Techniques (RETs) increases Isolated-dense bias and leaves very small process window for isolated transistor patterns. It implies that a very aggressive and also very delicate OPC work is required for these new generation devices. A novel measurement system which can compare CD SEM image with CAD data has been developed and we were able to systematically calibrate OPC modeling and verify modeling accuracy by connecting this measurement system with OPC tools. In this paper, the functions of the novel measurement system are presented and the application to the OPC calibration and OPC accuracy verification are presented. This novel measurement system was very useful for 2D model calibration. We were able to enhance OPC accuracy through this systematic OPC calibration and verification methodology.

Paper Details

Date Published: 10 May 2005
PDF: 7 pages
Proc. SPIE 5752, Metrology, Inspection, and Process Control for Microlithography XIX, (10 May 2005); doi: 10.1117/12.599728
Show Author Affiliations
Hyunjo Yang, Hynix Semiconductor Inc. (South Korea)
Jaeseung Choi, Hynix Semiconductor Inc. (South Korea)
Byungug Cho, Hynix Semiconductor Inc. (South Korea)
Byeongho Cho, Hynix Semiconductor Inc. (South Korea)
Donggyu Yim, Hynix Semiconductor Inc. (South Korea)
Jinwoong Kim, Hynix Semiconductor Inc. (South Korea)


Published in SPIE Proceedings Vol. 5752:
Metrology, Inspection, and Process Control for Microlithography XIX
Richard M. Silver, Editor(s)

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