Share Email Print

Proceedings Paper

The effect of mask substrate and mask process steps on patterned photomask flatness
Author(s): Kenneth Racette; Monica Barrett; Michael Hibbs; Max Levy
Format Member Price Non-Member Price
PDF $17.00 $21.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Photomask substrate, blank, and finished mask flatness are becoming more serious concerns for photomask fabrication. Most commercial and captive mask houses now use a combination of mask blanks at various flatness levels from >2.0um to <0.5um, measured as total indicated range, or TIR. As mask feature sizes are reduced, depth of focus becomes significantly smaller, driving the need for tighter flatness specifications. Photomask blank suppliers generally specify mask blank flatness based on measurements of quartz substrates before films are deposited. The mask substrates start with unique, non-flat shapes resulting from polishing and are further deformed by the stress of deposited films. Mask patterning, which removes some of the deposited films, has the potential to change the shape and flatness of the mask. The attachment of a pellicle and frame also has the potential to distort the mask. Since the goal of the mask maker is to provide a finished mask meeting all requirements, including flatness, it is important to understand the effects of each step in the flatness life of the photomask. This paper provides flatness data from the following process steps: quartz substrate, chromium coating, phase shifter coating, resist coating, patterned mask and pelliclized mask. A correlation is made of substrate and blank flatness and shape to finished mask flatness, with proposed practical guidelines for control of final mask flatness.

Paper Details

Date Published: 10 May 2005
PDF: 11 pages
Proc. SPIE 5752, Metrology, Inspection, and Process Control for Microlithography XIX, (10 May 2005); doi: 10.1117/12.599598
Show Author Affiliations
Kenneth Racette, IBM Microelectronics (United States)
Monica Barrett, IBM Microelectronics (United States)
Michael Hibbs, IBM Microelectronics (United States)
Max Levy, IBM Microelectronics (United States)

Published in SPIE Proceedings Vol. 5752:
Metrology, Inspection, and Process Control for Microlithography XIX
Richard M. Silver, Editor(s)

© SPIE. Terms of Use
Back to Top