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Proceedings Paper

Application of bi-layer resist on 70 nm node memory devices
Author(s): Yool Kang; Jin Hong; Shi-Yong Lee; Hyung-Rae Lee; Man-Hyoung Ryoo; Sang-Gyun Woo; Han-Ku Cho; Joo-Tae Moon
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Paper Abstract

Bi-Layer Resist (BLR) process has been developed as an alternative method to overcome the limit of Single-Layer Resist lithography. Compared to other methods such as Single-Layer Resist (SLR) and Multi-Layer Resist (MLR), BLR has distinct advantages in cost down effect and quick Turn-Around-Time (TAT) due to the reduced number of process steps. In addition, it yields acceptional improvement in the Line-Width Roughness (LWR) on smaller CD. We have obtained feasible results of dense line and space patterning on various devices, which has 70 nm design rule. In this paper, a scanner of NA 0.85 is used and then appropriate condition of dry etch without any grass defect is developed. We are certain that BLR process is a strong candidate approach for the extension technology of ArF lithography and has potentially applicable in various devices.

Paper Details

Date Published: 4 May 2005
PDF: 8 pages
Proc. SPIE 5753, Advances in Resist Technology and Processing XXII, (4 May 2005); doi: 10.1117/12.599484
Show Author Affiliations
Yool Kang, Samsung Electronics Co., Ltd. (South Korea)
Jin Hong, Samsung Electronics Co., Ltd. (South Korea)
Shi-Yong Lee, Samsung Electronics Co., Ltd. (South Korea)
Hyung-Rae Lee, Samsung Electronics Co., Ltd. (South Korea)
Man-Hyoung Ryoo, Samsung Electronics Co., Ltd. (South Korea)
Sang-Gyun Woo, Samsung Electronics Co., Ltd. (South Korea)
Han-Ku Cho, Samsung Electronics Co., Ltd. (South Korea)
Joo-Tae Moon, Samsung Electronics Co., Ltd. (South Korea)


Published in SPIE Proceedings Vol. 5753:
Advances in Resist Technology and Processing XXII
John L. Sturtevant, Editor(s)

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