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Proceedings Paper

EPL performance in 65-nm node metallization technology and beyond
Author(s): F. Koba; T. Tsuchida; H. Sakaue; K. Koike; J. Yamamoto; N. Iriki; H. Yamashita; S. Kageyama; T. Nasuno; E. Soda; K. Takeda; H. Kobayashi; F. Shoji; H. Okamura; Y. Matsubara; H. Arimoto
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Paper Abstract

We evaluate electron projection lithography (EPL) performance for a via layer at 65-nm and 45-nm technology nodes through the fabrication of a via-chain test element group (TEG) using EPL/ArF mix-and-match (M&M) lithography. The via-chain is prepared by tow-layer metallization using a Cu/low-k single damascene process. Here, Metal 1 (M1) and Metal 2 (M2) are patterned by using an ArF scanner, and Via 1 (V1) is patterned by using an EPL exposure system. For the EPL performance evaluation at 65-nm technology node, we utilized transmission electron microscope (TEM) and confirmed that a 100-nm via-chain is successfully fabricated and a yield of 94% is achieved. For an EPL performance evaluation at 45-nm technology node, also by using TEM, we confirmed that fabrication of a 70-nm via-chain with reasonable quality is feasible although with a lower yield. For our next step we are planning to carry out an EPL performance at 32-nm technology node by printing a via layer and a metal layer using a corresponding via-chain TEG. Here, M1, V1 and M2 will be patterned by using the EPL exposure system. Although an EPL development at 32-nm technology node is still at its early stages, a via-hole resist pattern of 50 nm and a lines and spaces (L/S) resist pattern of 45 nm have almost been completed. These results suggest that EPL is quite promising for meeting the back-end-of-line (BEOL) process requirement for 65-nm, 45-nm and also for 32-nm technology nodes.

Paper Details

Date Published: 6 May 2005
PDF: 8 pages
Proc. SPIE 5751, Emerging Lithographic Technologies IX, (6 May 2005); doi: 10.1117/12.599257
Show Author Affiliations
F. Koba, Semiconductor Leading Edge Technologies Inc. (Japan)
T. Tsuchida, Semiconductor Leading Edge Technologies Inc. (Japan)
H. Sakaue, Semiconductor Leading Edge Technologies Inc. (Japan)
K. Koike, Semiconductor Leading Edge Technologies Inc. (Japan)
J. Yamamoto, Semiconductor Leading Edge Technologies Inc. (Japan)
N. Iriki, Semiconductor Leading Edge Technologies Inc. (Japan)
H. Yamashita, Semiconductor Leading Edge Technologies Inc. (Japan)
S. Kageyama, Semiconductor Leading Edge Technologies Inc. (Japan)
T. Nasuno, Semiconductor Leading Edge Technologies Inc. (Japan)
E. Soda, Semiconductor Leading Edge Technologies Inc. (Japan)
K. Takeda, Semiconductor Leading Edge Technologies Inc. (Japan)
H. Kobayashi, Semiconductor Leading Edge Technologies Inc. (Japan)
F. Shoji, Semiconductor Leading Edge Technologies Inc. (Japan)
H. Okamura, Semiconductor Leading Edge Technologies Inc. (Japan)
Y. Matsubara, Semiconductor Leading Edge Technologies Inc. (Japan)
H. Arimoto, Semiconductor Leading Edge Technologies Inc. (Japan)


Published in SPIE Proceedings Vol. 5751:
Emerging Lithographic Technologies IX
R. Scott Mackay, Editor(s)

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