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Proceedings Paper

Effect of post development process for resist roughness
Author(s): Koutarou Sho; Tsuyoshi Shibata; Eishi Shiobara; Shinichi Ito
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Paper Abstract

Recently, gate length variation such as Line Width Roughness (LWR) is severe problem in MPU. The LWR of resist pattern is mainly due to resist material and optical contrast. However it is hard to improve these factors. Many techniques have reported to decrease LWR, but there were no reports which process was more effective for improvement on LWR. Some methods were considered to improve resist roughness. This paper discusses about LWR of ArF resist in gate layer of 65 nm node device. We tied post bake process after development to smooth resist pattern surface by its surface tension. Recess process of resist roughness by using a pattern shrink film was also investigated. LWR’s were 36% and 26% decreased by post baking process and recess process, respectively. Post bake temperature was near resist melting point. From the consideration of thermal flow process, distance of smoothing force by surface tension is considered about several hundreds nm. Pattern shrink film is using acid catalysis reaction, so its distance of smoothing by acid diffusion is considered about one hundred nm. It is considered that effect of post development process is caused by distance of smoothing force. Moreover influence of those processes for lithographic performance will be evaluated.

Paper Details

Date Published: 4 May 2005
PDF: 8 pages
Proc. SPIE 5753, Advances in Resist Technology and Processing XXII, (4 May 2005); doi: 10.1117/12.599209
Show Author Affiliations
Koutarou Sho, Toshiba Corp. (Japan)
Tsuyoshi Shibata, Toshiba Corp. (Japan)
Eishi Shiobara, Toshiba Corp. (Japan)
Shinichi Ito, Toshiba Corp. (Japan)


Published in SPIE Proceedings Vol. 5753:
Advances in Resist Technology and Processing XXII
John L. Sturtevant, Editor(s)

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