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Proceedings Paper

Study of EB-tree
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Paper Abstract

Direct write electron-beam (e-beam) lithography, which has the maskless patterning capability and the quick turnaround for new device designs and design changes, has been applied to making the engineering samples for the development of the System on Chip products (SoC). Using the e-beam lithography to the multilevel interconnect metal was known to be evaluate in view of cost and throughput. In the case of the high-energy e-beam lithography, however, the backscattered electron from the metal caused a significant proximity effect. Authors evaluated the e-beam proximity effect using the accelerating voltage 50keV on some multi-level interconnect metal structures which consist in tungsten wiring, or Cu wiring. It was found that the backscattering range and the ratio of the backscattering energy to the incident energy depend on the thickness of metal, but also on the distance from the resist to the metal. Therefore authors propose a new method of evaluating e-beam lithography property, concept of "EB-tree". That indicates the wafer backscatter property that has heavy metal wiring using e-beam lithography. EB-tree shows the relations of wafer backscatter range and heavy metal thickness, ratio of the backscattering energy and heavy metal thickness. EB-tree could show wafer property cause of lower levels layout, understructure metal wiring, that must be taken into account when e-beam lithography.

Paper Details

Date Published: 6 May 2005
PDF: 8 pages
Proc. SPIE 5751, Emerging Lithographic Technologies IX, (6 May 2005); doi: 10.1117/12.598923
Show Author Affiliations
Kazuo Tawarayama, Toshiba Corp. Semiconductor Co. (Japan)
Shunko Magoshi, Toshiba Corp. Semiconductor Co. (Japan)
Shinji Sato, Toshiba Corp. Semiconductor Co. (Japan)
Masayuki Hatano, Toshiba Corp. Semiconductor Co. (Japan)


Published in SPIE Proceedings Vol. 5751:
Emerging Lithographic Technologies IX
R. Scott Mackay, Editor(s)

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