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Proceedings Paper

First microprocessors with immersion lithography
Author(s): D. Gil; T. Bailey; D. Corliss; M. J. Brodsky; P. Lawson; M. Rutten; Z. Chen; N. Lustig; T. Nigussie; K. Petrillo; C. Robinson
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Paper Abstract

Immersion lithography has emerged as the leading solution for semiconductor manufacturing for the 45nm node. With the emergence of the first full-field immersion lithography scanners, the technology is getting ready to be inserted in semiconductor manufacturing facilities throughout the world. In the initial implementation phase, the enhanced depth-of-focus provided by immersion will be utilized to mitigate the narrow process window in which leading-edge semiconductor manufacturing has been forced to operate, creating a new set of opportunities.1 The area of defects, however, has remained of critical concern for this technology. It has become clear that the ultimate proof of the readiness of immersion, especially from a defect point of view, must be attained by integrating the immersion process in a production environment. In this paper, we demonstrate that fully functional 90nm PowerPCTM microprocessors have been fabricated using immersion lithography for one of the litho-critical via levels, achieving the goal of confirming that immersion lithography is a viable manufacturing solution. For this demonstration, we utilized the AT1150i (ASML), currently at Albany NanoTech (NY). The system is a 0.75 NA full-field 193nm projection (4x) scanner. We were able to achieve lithographic and overlay performance that exceeded product specifications while achieving a sufficiently low defect count so as to have yielding chips and modules. We have classified the leading types of defects that can be attributed to the immersion process and have assessed their processing impact. Electrical characterization of the integrated devices confirmed full functionality at both wafer final test (WFT) and module test (MT).

Paper Details

Date Published: 12 May 2004
PDF: 10 pages
Proc. SPIE 5754, Optical Microlithography XVIII, (12 May 2004); doi: 10.1117/12.598855
Show Author Affiliations
D. Gil, IBM SRDC (United States)
T. Bailey, IBM SRDC (United States)
D. Corliss, IBM SRDC (United States)
M. J. Brodsky, IBM SRDC (United States)
P. Lawson, IBM SRDC (United States)
M. Rutten, IBM SRDC (United States)
Z. Chen, IBM SRDC (United States)
N. Lustig, IBM SRDC (United States)
T. Nigussie, IBM SRDC (United States)
K. Petrillo, IBM SRDC (United States)
C. Robinson, IBM SRDC (United States)


Published in SPIE Proceedings Vol. 5754:
Optical Microlithography XVIII
Bruce W. Smith, Editor(s)

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