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Proceedings Paper

DFM in practice: results of a three way partnership between a leading fabless design house, foundry, and EDA company to implement alternating-phase shift mask (Alt-PSM) on a 90-nm FPGA chip
Author(s): Chun-Chi Yu; Ming-Feng Shieh; Erick Liu; Benjamin Lin; Henry Lin; Manoj Chacko; Xiaoyang Li; Wen-Kang Lei; Jonathan Ho; Xin Wu
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Paper Abstract

At the sub 90nm nodes, resolution enhancement techniques (RETs) such as optical proximity correction (OPC), phase-shifting masks (PSM), sub-resolution assist features (SRAF) have become essential steps in the post-physical verification 'Mask Synthesis' process and a key component of design for manufacturing (DFM). Several studies have been conducted and the results have been published on the implication and application of the different types of RETs on mask printability and costs. More specifically, double-exposure-based, dark-field, alternating PSM (Alt-PSM) technology has received lot of attention with respect to the mask manufacturing challenges and its implementation into a production flow, despite its yield and critical dimension (CD) control superiority. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a matured, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. What follows is an in-depth review of the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.

Paper Details

Date Published: 5 May 2005
PDF: 12 pages
Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005); doi: 10.1117/12.598838
Show Author Affiliations
Chun-Chi Yu, UMC (Taiwan)
Ming-Feng Shieh, UMC (Taiwan)
Erick Liu, UMC (Taiwan)
Benjamin Lin, UMC (Taiwan)
Henry Lin, Synopsys Inc. (United States)
Manoj Chacko, Synopsys Inc. (United States)
Xiaoyang Li, Synopsys Inc. (United States)
Wen-Kang Lei, Synopsys Inc. (United States)
Jonathan Ho, Xilinx Inc. (United States)
Xin Wu, Xilinx Inc. (United States)

Published in SPIE Proceedings Vol. 5756:
Design and Process Integration for Microelectronic Manufacturing III
Lars W. Liebmann, Editor(s)

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