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Proceedings Paper

Study of segmented overlay mark fidelity based on electrical property of device
Author(s): Akiyuki Minami; Sachiko Yabe; Takashi Nasuno; Yoshihisa Matsubara; Koichiro Tsujita
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Paper Abstract

Pattern placement error (PPE) of device pattern and overlay mark does not necessarily coincide. So it is important to measure PPE of device pattern accurately for optimizing overlay mark design. But it has been hard. To resolve this problem a new method has been developed. As a device pattern via chain pattern is used that consists of 1st metal, via, and 2nd metal layers. The electrical resistance is almost determined by the contact area of metal and via which depend on their mutual overlay. Since the resistance is inversely proportional to the contact area, the resistance changes sharply as the overlay error becomes large. With the characteristic the fine measurement accuracy of about 1nm has been gotten. We evaluate the relation of PPE between the device pattern and various types of overlay marks such as box in box mark and device size-segmented mark on 65nm node Cu interconnect. As a result, it has been confirmed that the device size-segmented mark most represents the PPE of device pattern at various aberrations.

Paper Details

Date Published: 10 May 2005
PDF: 12 pages
Proc. SPIE 5752, Metrology, Inspection, and Process Control for Microlithography XIX, (10 May 2005); doi: 10.1117/12.598654
Show Author Affiliations
Akiyuki Minami, Semiconductor Leading Edge Technologies, Inc. (Japan)
Sachiko Yabe, Semiconductor Leading Edge Technologies, Inc. (Japan)
Takashi Nasuno, Semiconductor Leading Edge Technologies, Inc. (Japan)
Yoshihisa Matsubara, Semiconductor Leading Edge Technologies, Inc. (Japan)
Koichiro Tsujita, Semiconductor Leading Edge Technologies, Inc. (Japan)


Published in SPIE Proceedings Vol. 5752:
Metrology, Inspection, and Process Control for Microlithography XIX
Richard M. Silver, Editor(s)

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