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Proceedings Paper

Lithography manufacturing implementation for 65 nm and 45 nm nodes with model-based scattering bars using IML technology
Author(s): Michael Hsu; Doug Van Den Broeke; Tom Laidig; Kurt E. Wampler; Uwe Hollerbach; Robert Socha; J. Fung Chen; Stephen Hsu; Xuelong Shi
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Paper Abstract

Scattering Bars (SB) OPC, together with optimized illumination, is no doubt one of the critical enablers for low k1lithography manufacturing. (1) The manufacturing implementation of SB so far has been mainly based on rule-based approach. While thiis has been working well, a more effective model-based approach is much more desired lithographically for manufacturing at 65nm and 45nm nodes. This is necessary to ensure sufficient process margin using hyper NA for patterning random IC design. In our model-based SB (M-SB) OPC implementation, we have based on the patented IML. Technology from ASML MaskTools.(2,3) In this report, we use both dark field contact hole and clear field poly gate mask to demonstrate this implementation methodology. It is also quite applicable for dark field trench masks, such as local interconnect mask with damascene metal. For our full-chip implementation flow, the first step is to determine the critical design area and then to proceed with NA and illumination optimization. We show that, using LithoCruiser, we are able to select the best NA in combination with optimum illumination via a Diffraction Optical Element (DOE). The decision to use a custom DOE or one from the available DOE library from ASML can be made based on predicted process performance and cost effectiveness. With optimized illumination, it is now possible for MaskWeaver to construct an interference map for the full-chip mask pattern. Utilizing the interference map, M-SB OPC is generated. Next, model OPC can be applied with the presence of M-SB for the entire chip. It is important to note here, that from our experience, the model OPC must be calibrated with the presence of SB in order to achieve the desired accuracy. We report the full-chip processing benchmark using MaskWeaver to apply both M-SB and model OPC. For actual patterning performance, we have verified the full chip OPC treatment using SLiC, a DFM tool from Cadence. This implementation methodology can be applied to binary chrome mask, attenuated PSM, and CPL.

Paper Details

Date Published: 12 May 2004
PDF: 13 pages
Proc. SPIE 5754, Optical Microlithography XVIII, (12 May 2004); doi: 10.1117/12.598589
Show Author Affiliations
Michael Hsu, ASML MaskTools, Inc. (United States)
Doug Van Den Broeke, ASML MaskTools, Inc. (United States)
Tom Laidig, ASML MaskTools, Inc. (United States)
Kurt E. Wampler, ASML MaskTools, Inc. (United States)
Uwe Hollerbach, ASML MaskTools, Inc. (United States)
Robert Socha, ASML MaskTools, Inc. (United States)
J. Fung Chen, ASML MaskTools, Inc. (United States)
Stephen Hsu, ASML MaskTools, Inc. (United States)
Xuelong Shi, ASML MaskTools, Inc. (United States)


Published in SPIE Proceedings Vol. 5754:
Optical Microlithography XVIII
Bruce W. Smith, Editor(s)

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