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Proceedings Paper

Submicron defect detection standard for patterned wafer inspection systems
Author(s): Daniel V. Grelinger
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Paper Abstract

Automated defect detection equipment have been used extensively for patterned wafer inspection in the semiconductor industry. These systems are used to find a variety of patterning and process defects on silicon wafers, before device completion, so that action may be directed toward eliminating the cause of the defects. The method of detection that each type of inspection system uses varies significantly, as does its performance when inspecting an assortment of patterns and materials. Standard materials to quantify the performance of inspection systems are not available, and as a result, a myriad of pseudo-standards are used to measure and compare performance. The suppliers of patterned wafer inspection systems routinely provide `standards' with which to test and qualify their equipment. Generally, programmed `defects' embedded within generic test patterns are reproduced from a mask onto a silicon wafer using standard deposition, lithographic, and etch processes. These `standard test wafers' are of limited value for the task of quantifying the performance of the inspection equipment for several reasons. The photolithographic techniques that are most often used to produce programmed `defects' on test wafers provide for the construction of only one broad type of `defect.' This one type represents a very small sample of the variety of real defects that the detection system is expected to find during actual wafer inspections. Therefore, it is not possible to quantify the performance of the system relating to the other types of real defects. The limitations of the lithography prevent precise control over the shape and dimensions, (and even the reproduction), of sub-micron `defects.' The patterns and materials used for the `standard' are generally not representative of actual semiconductor product wafers, on which real inspections are to be done. Test patterns are generally single level, and high-contrast, with relatively large geometries. `Defects' are reproduced in the same plane as the test pattern, and at the same thickness as the material in which the pattern is being defined. Whereas the sensitivity performance of the detection system may be suitable on the test pattern, relative performance during inspections on real product wafers with complex multilevel patterns of sub-micron geometries cannot be inferred. An alternate method for producing and qualifying `standards' for patterned wafer defect detection system evaluation that represents a significant enhancement over existing methods has been developed. This method utilizes a focused ion beam, (FIB), to fabricate the `defects' directly onto real production semiconductor wafers. The use of an FIB to place milled and deposited `defects' onto a patterned wafer is a new application of this technology. The capabilities of the FIB provide unique potential to address many of the common problems with existing patterned wafer defect standard generation and application.

Paper Details

Date Published: 1 June 1992
PDF: 9 pages
Proc. SPIE 1673, Integrated Circuit Metrology, Inspection, and Process Control VI, (1 June 1992); doi: 10.1117/12.59809
Show Author Affiliations
Daniel V. Grelinger, AT&T Microelectronics and SEMATECH (United States)


Published in SPIE Proceedings Vol. 1673:
Integrated Circuit Metrology, Inspection, and Process Control VI
Michael T. Postek, Editor(s)

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