Share Email Print
cover

Proceedings Paper

Advanced wafer manufacturing control for yield improvement in the ULSI age
Author(s): Takafumi Yoshida; Nobuaki Hayashi; Louis Denes; Tokuhisa Ito
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Primarily, this research focuses on a new technical approach to the solution of improving yield in the manufacture of super-flat wafers for ULSI. Secondarily, it introduces current and future concerns relating to the depth of focus issue as well as an overview of the general wafer manufacturing process. Ever-decreasing lithographic linewidths and ever increasing wafer diameter and site size are placing great demands on wafer makers to produce even flatter wafers to achieve the yields necessary for economical device production. Successful next- generation wafer production will rely heavily on proactive quality and manufacturing processes. Indeed, metrology is now being jointly developed to move flatness inspection from a final QC inspection to in-process, quasi-real time, analysis. The theoretical development and implementation of an advanced digital interferometer system into the actual wafer manufacturing process is described. An advanced, workstation-centered, Ethernet LAN interfaced, system is described. The flatness, and change in flatness, with respect to processing and time is accumulated, tracked, and controlled from the beginning of wafer preparation through final mirror polishing. Additionally, the influence of the polishing block (as used in the popular `wax-mount polishing') on overall wafer flatness is investigated. Finally, absolute wafer thickness as an additional process variable is introduced into the analysis.

Paper Details

Date Published: 1 June 1992
PDF: 12 pages
Proc. SPIE 1673, Integrated Circuit Metrology, Inspection, and Process Control VI, (1 June 1992); doi: 10.1117/12.59801
Show Author Affiliations
Takafumi Yoshida, Nippon Steel Corp. (Japan)
Nobuaki Hayashi, Nippon Steel Corp. (Japan)
Louis Denes, GCA Tropel (United States)
Tokuhisa Ito, General Signal Japan Corp. (Japan)


Published in SPIE Proceedings Vol. 1673:
Integrated Circuit Metrology, Inspection, and Process Control VI
Michael T. Postek, Editor(s)

© SPIE. Terms of Use
Back to Top