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Proceedings Paper

A hardware architecture for a context-adaptive binary arithmetic coder
Author(s): Subramania Sudharsanan; Adam Cohen
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Paper Abstract

The H.264 video compression standard uses a context-adaptive binary arithmetic coder (CABAC) as an entropy coding mechanism. While the coder provides excellent compression efficiency, it is computationally demanding. On typical general-purpose processors, it can take up to hundreds of cycles to encode a single bit. In this paper, we propose an architecture for a CABAC encoder that can easily be incorporated into system-on-chip designs for H.264 compression. The CABAC is inherently serial and we divide the problem into several stages to derive a design that can provide a throughput of two cycles per encoded bit. The engine proposed is capable of handling binarization of the syntactical elements and provides the coded bit-stream via a first-in first-out buffer. The design is implemented on an Altera FPGA platform that can run at 50 MHz enabling a 25 Mbps encoding rate.

Paper Details

Date Published: 8 March 2005
PDF: 9 pages
Proc. SPIE 5683, Embedded Processors for Multimedia and Communications II, (8 March 2005); doi: 10.1117/12.596811
Show Author Affiliations
Subramania Sudharsanan, Queen's Univ. (Canada)
Adam Cohen, Queen's Univ. (Canada)

Published in SPIE Proceedings Vol. 5683:
Embedded Processors for Multimedia and Communications II
Subramania Sudharsanan; V. Michael Bove; Sethuraman Panchanathan, Editor(s)

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