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Proceedings Paper

Monitoring of cache miss rates for accurate dynamic voltage and frequency scaling
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Paper Abstract

Modern mobile processors offer dynamic voltage and frequency scaling, which can be used to reduce the energy requirements of embedded and real-time applications by exploiting idle CPU resources, while still maintaining all applications' real-time characteristics. However, accurate predictions of task run-times are key to computing the frequencies and voltages that ensure that all tasks' real-time constraints are met. Past work has used feedback-based approaches, where applications' past CPU utilizations are used to predict future CPU requirements. Inaccurate predictions in these approaches can lead to missed deadlines, less than expected energy savings, or large overheads due to frequent voltage and frequency changes. Previous solutions ignore other `indicators' of future CPU requirements, such as the frequency of I/O operations, memory accesses, or interrupts. This paper addresses this shortcoming for memory-intensive applications, where measured task run-times and cache miss rates are used as feedback for accurate run-time predictions. Cache miss rates indicate the frequency of memory accesses and enable us to derive the latencies introduced by these operations. The results shown in this paper indicate improvements in the number of deadlines met and the amount of energy saved.

Paper Details

Date Published: 17 January 2005
PDF: 5 pages
Proc. SPIE 5680, Multimedia Computing and Networking 2005, (17 January 2005); doi: 10.1117/12.590806
Show Author Affiliations
Leo C. Singleton, Georgia Institute of Technology (United States)
Christian Poellabauer, Univ. of Notre Dame (United States)
Karsten Schwan, Georgia Institute of Technology (United States)


Published in SPIE Proceedings Vol. 5680:
Multimedia Computing and Networking 2005
Surendar Chandra; Nalini Venkatasubramanian, Editor(s)

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