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Proceedings Paper

Parallel image compression circuit for high-speed cameras
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Paper Abstract

In this paper, we propose 32 parallel image compression circuits for high-speed cameras. The proposed compression circuits are based on a 4 x 4-point 2-dimensional DCT using a DA method, zigzag scanning of 4 blocks of the 2-D DCT coefficients and a 1-dimensional Huffman coding. The compression engine is designed with FPGAs, and the hardware complexity is compared with JPEG algorithm. It is found that the proposed compression circuits require much less hardware, leading to a compact high-speed implementation of the image compression circuits using parallel processing architecture. The PSNR of the reconstructed image using the proposed encoding method is better than that of JPEG at the region of low compression ratio.

Paper Details

Date Published: 25 February 2005
PDF: 12 pages
Proc. SPIE 5671, Real-Time Imaging IX, (25 February 2005); doi: 10.1117/12.588030
Show Author Affiliations
Yukinari Nishikawa, Univ. of Shizuoka (Japan)
Shoji Kawahito, Univ. of Shizuoka (Japan)
Toru Inoue, Photron Ltd. (Japan)

Published in SPIE Proceedings Vol. 5671:
Real-Time Imaging IX
Nasser Kehtarnavaz; Phillip A. Laplante, Editor(s)

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