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Proceedings Paper

Embedded architecture for fast implementation of H.264 subpixel interpolation
Author(s): Philip P. Dang
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Paper Abstract

H.264 is the latest video compression standard. Its rate distortion is greatly improved comparing to the MPEG-1, MPEG-2, MPEG-4, H.261 and H.263. Among many features of H.264, sub-pixel motion compensation is one of the factors that make H.264 a better coding scheme. H.264 implements both half-pixel interpolation and quarter-pixel interpolation. The computational complexity of sub-pixel motion compensation is therefore high. This paper presents an efficient VLSI architecture for fast implementation of sub-pixel interpolation of H.264. Several techniques are designed to reduce the number of memory access and accelerate the interpolation computations.

Paper Details

Date Published: 8 March 2005
PDF: 7 pages
Proc. SPIE 5683, Embedded Processors for Multimedia and Communications II, (8 March 2005); doi: 10.1117/12.586053
Show Author Affiliations
Philip P. Dang, STMicroelectronics Inc. (United States)


Published in SPIE Proceedings Vol. 5683:
Embedded Processors for Multimedia and Communications II
Subramania Sudharsanan; V. Michael Bove; Sethuraman Panchanathan, Editor(s)

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