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Proceedings Paper

Design of a systolic VLSI chip for computing scale space
Author(s): Sanjay Nichani; N. Ranganathan
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Paper Abstract

In this paper we describe the design and implementation of a systolic VLSI chip for computing scale space. The hardware can also be used for Gaussian filtering and Laplacian of Gaussian edge detection. The chip is based on an architecture proposed earlier. The algorithm and the architecture exploit a high degree of pipelining and parallelism in order to obtain high speed, efficiency, and throughput. The hardware organization of a processor cell is simple enough that the entire systolic array can be realized as a single chip system. A prototype CMOS VLSI chip implementing a single processor cell was designed, fabricated, and tested. Based on the estimates obtained from the prototype chip, a real life chip is expected to operate at a rate of 40 MHz. The chip can process a 512 X 512 gray-level image in about 0.006 seconds and a 1000 X 1000 gray-level image in 0.012 seconds which is much faster than other systems reported in the literature.

Paper Details

Date Published: 1 March 1992
PDF: 11 pages
Proc. SPIE 1708, Applications of Artificial Intelligence X: Machine Vision and Robotics, (1 March 1992); doi: 10.1117/12.58568
Show Author Affiliations
Sanjay Nichani, Inex Vision Systems (United States)
N. Ranganathan, Univ. of South Florida (United States)


Published in SPIE Proceedings Vol. 1708:
Applications of Artificial Intelligence X: Machine Vision and Robotics
Kevin W. Bowyer, Editor(s)

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