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Proceedings Paper

Instruction-level power dissipation in the Intel XScale embedded microprocessor
Author(s): Ankush Varma; Eric Debes; Igor Kozintsev; Bruce Jacob
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Paper Abstract

We present an instruction-level power dissipation model of the Intel XScale microprocessor. The XScale implements the ARM ISA, but uses an aggressive microarchitecture and a SIMD Wireless MMX co-processor to speed up execution of multimedia workloads in the embedded domain. Instruction-Level power modelling was first proposed by Tiwari et. al in 1994. Adaptations of this model have been found to be applicable to simple ARM processors. Research also shows that instructions can be clustered into groups with similar energy characteristics. We adapt these methodologies to the significantly more complex XScale processor. We characterize the processor in terms of the energy costs of opcode execution, operand values, pipeline stalls etc. through accurate measurements on hardware. This instruction-based (rather than microarchitectural) approach allows us to build a high-speed power-accurate simulator that runs at MIPS-range speeds, while achieving accuracy better than 5%. The processor core accounts only for a portion of overall power consumption, and we move beyond the core to explore the issues involved in building a SystemC simulation framework that models power dissipation of complete systems quickly, flexibly and accurately.

Paper Details

Date Published: 8 March 2005
PDF: 8 pages
Proc. SPIE 5683, Embedded Processors for Multimedia and Communications II, (8 March 2005); doi: 10.1117/12.585564
Show Author Affiliations
Ankush Varma, Univ. of Maryland/College Park (United States)
Intel Labs. (United States)
Eric Debes, Intel Labs. (United States)
Igor Kozintsev, Intel Labs. (United States)
Bruce Jacob, Univ. of Maryland/College Park (United States)


Published in SPIE Proceedings Vol. 5683:
Embedded Processors for Multimedia and Communications II
Subramania Sudharsanan; V. Michael Bove Jr.; Sethuraman Panchanathan, Editor(s)

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