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Proceedings Paper

Implementation of reconfigurable time delay digital tanlock loop
Author(s): Mahmoud A. Al-Qutayri; Saleh R. Al-Araji; Nawaf I. Al-Moosa
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Paper Abstract

In this paper, a first order TDTL system is designed, simulated and implemented on a reconfigurable FPGA system. Initially the loop was designed and simulated using Matlab/Simulink. Subsequently some novel modifications were introduced to the TDTL in order to allow an optimized reconfigurable implementation, which eases the design process and allows for dynamic parameter and design modifications. The reconfigurable TDTL was tested in real time conditions under the same operating conditions of the simulated loop. Comparison between the simulated and real time results indicate a high degree of correlation, making the loop attractive for various practical applications.

Paper Details

Date Published: 28 February 2005
PDF: 8 pages
Proc. SPIE 5649, Smart Structures, Devices, and Systems II, (28 February 2005); doi: 10.1117/12.582304
Show Author Affiliations
Mahmoud A. Al-Qutayri, Etisalat College of Engineering (United Arab Emirates)
Emirates Telecommunications Corp. (United Arab Emirates)
Saleh R. Al-Araji, Etisalat College of Engineering (United Arab Emirates)
Emirates Telecommunications Corp. (United Arab Emirates)
Nawaf I. Al-Moosa, Etisalat College of Engineering (United Arab Emirates)
Emirates Telecommunications Corp. (United Arab Emirates)


Published in SPIE Proceedings Vol. 5649:
Smart Structures, Devices, and Systems II
Said F. Al-Sarawi, Editor(s)

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