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Proceedings Paper

An integrable low-cost hardware random number generator
Author(s): Damith C. Ranasinghe; Daihyun Lim; Srinivas Devadas; Behnam Jamali; Zheng Zhu; Peter H. Cole
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Paper Abstract

A hardware random number generator is different from a pseudo-random number generator; a pseudo-random number generator approximates the assumed behavior of a real hardware random number generator. Simple pseudo random number generators suffices for most applications, however for demanding situations such as the generation of cryptographic keys, requires an efficient and a cost effective source of random numbers. Arbiter-based Physical Unclonable Functions (PUFs) proposed for physical authentication of ICs exploits statistical delay variation of wires and transistors across integrated circuits, as a result of process variations, to build a secret key unique to each IC. Experimental results and theoretical studies show that a sufficient amount of variation exits across IC’s. This variation enables each IC to be identified securely. It is possible to exploit the unreliability of these PUF responses to build a physical random number generator. There exists measurement noise, which comes from the instability of an arbiter when it is in a racing condition. There exist challenges whose responses are unpredictable. Without environmental variations, the responses of these challenges are random in repeated measurements. Compared to other physical random number generators, the PUF-based random number generators can be a compact and a low-power solution since the generator need only be turned on when required. A 64-stage PUF circuit costs less than 1000 gates and the circuit can be implemented using a standard IC manufacturing processes. In this paper we have presented a fast and an efficient random number generator, and analysed the quality of random numbers produced using an array of tests used by the National Institute of Standards and Technology to evaluate the randomness of random number generators designed for cryptographic applications.

Paper Details

Date Published: 28 February 2005
PDF: 13 pages
Proc. SPIE 5649, Smart Structures, Devices, and Systems II, (28 February 2005); doi: 10.1117/12.582255
Show Author Affiliations
Damith C. Ranasinghe, The Univ. of Adelaide (Australia)
Daihyun Lim, Massachusetts Institute of Technology (United States)
Srinivas Devadas, Massachusetts Institute of Technology (United States)
Behnam Jamali, The Univ. of Adelaide (Australia)
Zheng Zhu, The Univ. of Adelaide (Australia)
Peter H. Cole, The Univ. of Adelaide (Australia)


Published in SPIE Proceedings Vol. 5649:
Smart Structures, Devices, and Systems II
Said F. Al-Sarawi, Editor(s)

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