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Proceedings Paper

Lithography yield enhancement through optical rule checking
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Paper Abstract

Use of simulation-based printing verification prior to mask tapeout has become standard practice for mask layers printed with low-k1 lithography processes. At 90nm and above, this methodology has proven beneficial and sufficient for guaranteeing a usable mask. However, it is anticipated that at 65nm and below, a simulation at a single point within the process window may fail to capture all important marginal areas of a mask prior to tapeout. Modern lithography simulation tools are proven capable of accurately predicting printing behavior through process window. Unfortunately, due to long run times, use of such tools is restricted to small simulation areas. Recent developments in vectorial thin-film OPC models have enabled full process window prediction on large product die. Although such models are extremely fast compared to conventional lithography simulation tools, the prospect of simulating a full chip at multiple dose and focus points is quite daunting. In an effort to reduce the expected longer run times when simulating full chips at multiple focus and dose conditions, we have developed two flows which reduce the total run time enormously. These so-called pre-targeting flows are explained, and the limitations and future prospects of the flows are described.

Paper Details

Date Published: 27 January 2005
PDF: 12 pages
Proc. SPIE 5645, Advanced Microlithography Technologies, (27 January 2005); doi: 10.1117/12.577609
Show Author Affiliations
James C. Word, Mentor Graphics Corp. (United States)
J. Andres Torres, Mentor Graphics Corp. (United States)
Thomas Roessler, Infineon Technologies AG (Germany)
Neal Lafferty, Mentor Graphics Corp./IMEC (Belgium)
Shumay Shang, Mentor Graphics Corp. (United States)


Published in SPIE Proceedings Vol. 5645:
Advanced Microlithography Technologies
Yangyuan Wang; Jun-en Yao; Christopher J. Progler, Editor(s)

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