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Proceedings Paper

Circuit model of double photodiodes for high-speed OEIC receivers
Author(s): Lu-Hong Mao; Yongquan Chen; Wei Li; Min Chen; Huilai Liang; Shi-lin Zhang; Weilian Guo
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Paper Abstract

Photo-generated carriers' transmission delay of a CMOS-Process-Compatible double photo-diode (DPD) is analyzed by using device simulation in this paper. The carriers' transmission delay of a DPD in CMOS N-well process consists of three parts: the delay in the P+ region, in the depletion region and in the N-well. The DPD equivalent circuit model, including photo-generated carriers' transmission delay, is given by means of device simulation. By comparing with different depth of the N-well and different area of the DPD, the delay of the diffusion part in the N-well and the delay of the junction capacitance are the most significant factors to determine the delay time of a DPD. In addition, the diffusion delay is relative to the depth, the doping concentration of the N-well and the bias. Adopting smaller size CMOS process is of benefit to improving the speed due to the shallow well, nevertheless the shallow well can cause the responsivity reduce. The responsivity reduce can be compensated by increasing the junction area.

Paper Details

Date Published: 17 January 2005
PDF: 8 pages
Proc. SPIE 5644, Optoelectronic Devices and Integration, (17 January 2005); doi: 10.1117/12.574735
Show Author Affiliations
Lu-Hong Mao, Tianjin Univ. (China)
Yongquan Chen, Tianjin Univ. (China)
Wei Li, Tianjin Univ. (China)
Min Chen, Tianjin Univ. (China)
Huilai Liang, Tianjin Univ. (China)
Shi-lin Zhang, Tianjin Univ. (China)
Weilian Guo, Tianjin Univ. (China)

Published in SPIE Proceedings Vol. 5644:
Optoelectronic Devices and Integration
Hai Ming; Xuping Zhang; Maggie Yihong Chen, Editor(s)

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