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Proceedings Paper

Self-alignment method by buried mask implantation for double gate MOS and nanodevices fabrication
Author(s): Remy Charavel; Jean-Pierre Raskin
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Paper Abstract

Two methods to build submicronic self-aligned devices based on SOI MOS technology have been studied. The foreseen application of these techniques is the fabrication of self-aligned double gate SOI MOS transistors. Both of these methods make use of the implantation of a buried mask underneath the active silicon layer and aligned with the top gate. The mask is revealed by a selective etching between doped and undoped polysilicon. In one case Tetra-methyl Ammonium hydroxide solution (TMAH) is used to create a negative mask, etching the undoped zones. In the second case, a positive mask is revealed in a solution made of Hydrofluoric acid, Nitric acid and Acetic acid (HNA), etching the doped zones. Once the mask is revealed, the process differs from a normal CMOS process by the addition of two Chemical Mechanical Polishing (CMP) and bonding steps. The realized demonstrator proves the feasibility of both the positive and negative buried mask.

Paper Details

Date Published: 19 January 2005
PDF: 11 pages
Proc. SPIE 5592, Nanofabrication: Technologies, Devices, and Applications, (19 January 2005); doi: 10.1117/12.572660
Show Author Affiliations
Remy Charavel, Univ. Catholique de Louvain (Belgium)
Jean-Pierre Raskin, Univ. Catholique de Louvain (Belgium)


Published in SPIE Proceedings Vol. 5592:
Nanofabrication: Technologies, Devices, and Applications
Warren Y-C. Lai; Stanley Pau; O. Daniel Lopez, Editor(s)

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