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Proceedings Paper

Accelerating yield ramp through design and manufacturing collaboration
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Paper Abstract

Ramping an integrated circuit from first silicon bring-up to production yield levels is a challenge for all semiconductor products on the path to profitable market entry. Two approaches to accelerating yield ramp are presented. The first is the use of laser mask writers for fast throughput, high yield, and cost effective pattern transfer. The second is the use of electrical test to find a defect and identify the physical region to probe in failure analysis that is most likely to uncover the root cause. This provides feedback to the design team on modifications to make to the design to avoid the yield issue in a future tape-out revision. Additionally, the process parameter responsible for the root cause of the defect is forward annotated through the design, mask and wafer coordinate systems so it can be monitored in-line on subsequent lots of the manufacturing run. This results in an improved recipe for the manufacturing equipment to potentially prevent the recurrence of the defect and raise yield levels on the following material. The test diagnostics approach is enabled by the seamless traceability of a feature across the design, photomask and wafer, made possible by a common data model for design, mask pattern generation and wafer fabrication.

Paper Details

Date Published: 6 December 2004
PDF: 9 pages
Proc. SPIE 5567, 24th Annual BACUS Symposium on Photomask Technology, (6 December 2004); doi: 10.1117/12.572591
Show Author Affiliations
Robin C. Sarma, Cadence Design Systems, Inc. (United States)
Huixiong Dai, Applied Materials, Inc. (United States)
Michael C. Smayling, Applied Materials, Inc. (United States)
Michael P. Duane, Applied Materials, Inc. (United States)


Published in SPIE Proceedings Vol. 5567:
24th Annual BACUS Symposium on Photomask Technology
Wolfgang Staud; J. Tracy Weed, Editor(s)

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