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Proceedings Paper

Hardware accelerator for linguistic data processing
Author(s): Marian S. Stachowicz; Janos Grantner; Larry L. Kinney
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Paper Abstract

A hardware accelerator that performs fuzzy learning, fuzzy inference, and defuzzification strategy computations is presented in this paper. The hardware is based on two-valued logic. A universal space of 25 elements with five levels each is supported. To achieve a high processing rate for real-time applications, the basic units of the accelerator are connected in a four-level pipeline. The accelerator can receive two parallel fuzzy data as inputs. At a clock rate of 20 MHz, the accelerator can perform 800,000 fuzzy logic inferences per second on multidimensional fuzzy data.

Paper Details

Date Published: 1 February 1992
PDF: 7 pages
Proc. SPIE 1607, Intelligent Robots and Computer Vision X: Algorithms and Techniques, (1 February 1992); doi: 10.1117/12.57080
Show Author Affiliations
Marian S. Stachowicz, Univ. of Minnesota (United States)
Janos Grantner, Univ. of Minnesota (United States)
Larry L. Kinney, Univ. of Minnesota (United States)


Published in SPIE Proceedings Vol. 1607:
Intelligent Robots and Computer Vision X: Algorithms and Techniques
David P. Casasent, Editor(s)

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