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Proceedings Paper

FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments
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Paper Abstract

The paper describes a behavioral model of fast, pipeline sorter dedicated to electronic triggering applications in the experiments of high energy physics (HEP). The sorter was implemented in FPGA for the RPC Muon Detector of CMS experiment (LHC accelerator, CERN) and for Backing Calorimeter (BAC) in ZEUS experiment (HERA accelerator, DESY). A general principle of the applied sorting algorithm was presented. The implementation results were debated in detail for chosen FPGA chips by ALTERA and XILINX manufactures. The realization costs have been calculated as function of system parameters.

Paper Details

Date Published: 22 July 2004
PDF: 10 pages
Proc. SPIE 5484, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments II, (22 July 2004); doi: 10.1117/12.568878
Show Author Affiliations
Krzysztof T. Pozniak, Warsaw Univ. of Technology (Poland)


Published in SPIE Proceedings Vol. 5484:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments II
Ryszard S. Romaniuk, Editor(s)

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