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Proceedings Paper

Towards systematic CD process control for e-beam lithography
Author(s): Christian K. Kalus
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Paper Abstract

The paper proposes a method to mitigate the ever tighter requirements for mask CD uniformity. The basic idea is simple. As the mask error enhancement factor (MEEF) soars at low k1 values with pitches getting smaller it sould be possible to alleviate the problem given there is a way to increase the pitch. For highly repetitive layouts like cell fields of DRAMs the solution is rather straightforward. One has to find the next larger pitch in the layout and divide the layout into sublayers. Those sub-layers are written into separate reticles for subsequent exposure. In consequence, the method will lead to double exposure in case two reticles have been generated. The simplest example is an array of lines and spaces with equal pitch. An almost trivial example, a regular square contact array, results in two equal checkerboards. The diagonal (1,1) in the square array is the second smallest pitch in a square array. To fully cover a square array requires two checkerboards separated by the base vector (1,0) of the original lattice. These two checkerboards will subsequently be printed by a double exposure. It is obvious that the pitch can be increased by choosing larger displacements at the cost of more sub-layers. Doubling the pitch, which makes manufacturing of masks a lot easier, would require four reticles, hence four exposures. The edges and corners of regular arrays print significantly different as the MEEF is position dependent. It can be expected that increasing the pitch is also beneficial in the sense that it levels off the MEEF variance. It will be investigated how much the common process window increases. The applicability of said method is obvious for memory layouts. It can however, be extended to semi-periodic or even random layouts. Its value depends primarily on the density of the layout and on the k1 value. Its potential uses comes in only at the leading edge of lithography where the MEEF starts to become a real pain for the mask maker. Simulation results will be shown as well as calculations of the process latitude before and after dividing the layout.

Paper Details

Date Published: 2 June 2004
PDF: 7 pages
Proc. SPIE 5504, 20th European Conference on Mask Technology for Integrated Circuits and Microcomponents, (2 June 2004); doi: 10.1117/12.568025
Show Author Affiliations
Christian K. Kalus, SIGMA-C GmbH (Germany)

Published in SPIE Proceedings Vol. 5504:
20th European Conference on Mask Technology for Integrated Circuits and Microcomponents
Uwe F. W. Behringer, Editor(s)

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