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Proceedings Paper

RTP for advanced CMOS process integration
Author(s): Mehrdad M. Moslehi; John Kuehne; Lino Velo; David Yin; Dick Yeakley; Steve S.H. Huang; Rhett Barry Jucha; Terence Breedijk
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Paper Abstract

Twelve rapid thermal processes have been developed for over fifteen critical thermal fabrication steps in a sub-0.50 p.m CMOS technology. These processes include dielectric growth (dry and wet rapid thermal oxidations), thermal anneals (source/drain & gate anneals, CMOS well formation, TiN/TiSi2 react, and forming gas anneal), rapid thermal chemical-vapor deposition (amorphous silicon, polysilicon, tungsten, silicon dioxide, and silicon nitride), and in-situ dry cleaning. The pro­ cess temperature range of these rapid thermal processing fabrication steps extends between 400°C and 1100°C. Complete sub-0.50 p.m CMOS process integration has been successfully demonstrated in a single-wafer minifactory consisting of all-RTP/no-furnace thermal processing.

Paper Details

Date Published: 1 February 1992
PDF: 14 pages
Proc. SPIE 1595, Rapid Thermal and Integrated Processing, (1 February 1992); doi: 10.1117/12.56671
Show Author Affiliations
Mehrdad M. Moslehi, Texas Instruments Inc. (United States)
John Kuehne, Texas Instruments Inc. (United States)
Lino Velo, Texas Instruments Inc. (United States)
David Yin, Texas Instruments Inc. (United States)
Dick Yeakley, Texas Instruments Inc. (United States)
Steve S.H. Huang, Texas Instruments Inc. (United States)
Rhett Barry Jucha, Texas Instruments Inc. (United States)
Terence Breedijk, Texas Instruments Inc. (United States)

Published in SPIE Proceedings Vol. 1595:
Rapid Thermal and Integrated Processing
Mehrdad M. Moslehi; Rajendra Singh; Dim-Lee Kwong, Editor(s)

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