Share Email Print

Proceedings Paper

Multilevel clustering fault model for IC manufacture
Author(s): Yu. I. Bogdanov; N. A. Bogdanova; A. V. Rudnev
Format Member Price Non-Member Price
PDF $17.00 $21.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

A hierarchical approach to the construction of compound distributions for process-induced faults in IC manufacture is proposed. Within this framework, the negative binomial distribution is treated as level-1 models. The hierarchical approach to fault distribution offers an integrated picture of how fault density varies from region to region within a wafer, from wafer to wafer within a batch, and so on. A theory of compound-distribution hierarchies is developed by means of generating functions. A study of correlations, which naturally appears in microelectronics due to the batch character of IC manufacture, is proposed. Taking these correlations into account is of significant importance for developing procedures for statistical quality control in IC manufacture. With respect to applications, hierarchies of yield means and yield probability-density functions are considered.

Paper Details

Date Published: 28 May 2004
PDF: 10 pages
Proc. SPIE 5401, Micro- and Nanoelectronics 2003, (28 May 2004); doi: 10.1117/12.562667
Show Author Affiliations
Yu. I. Bogdanov, OAO Angstrem (Russia)
N. A. Bogdanova, Moscow Institute of Electronic Technology (Russia)
A. V. Rudnev, OAO Angstrem (Russia)

Published in SPIE Proceedings Vol. 5401:
Micro- and Nanoelectronics 2003
Kamil A. Valiev; Alexander A. Orlikovsky, Editor(s)

© SPIE. Terms of Use
Back to Top