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Proceedings Paper

Self-timed adder performance and area modeling
Author(s): Rafael Kaliski; Anton Clarkson; Albert A. Liddicoat
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Paper Abstract

The current trend of exponential increases in clock frequency and an increase in the number of transistors per die causes increases in power consumption, total die area dedicated to the clock distribution network, and clock overhead incurred relative to the clock cycle time. Self-timed circuits may provide an alternative approach to synchronous circuit design that helps to reduce the negative characteristics of the high-speed clocks needed by synchronous circuits. This work presents a gate-level performance model and transistor-level performance, power and area approximations for both self-timed and static CMOS ripple-carry adders. These results show that for self-timed circuits with uniformly random input operands the average performance of a ripple-carry adder is logarithmic and improves performance by 37% with a 30% increase in the total transistor width as compared to a static CMOS ripple-carry adder.

Paper Details

Date Published: 26 October 2004
PDF: 10 pages
Proc. SPIE 5559, Advanced Signal Processing Algorithms, Architectures, and Implementations XIV, (26 October 2004); doi: 10.1117/12.560226
Show Author Affiliations
Rafael Kaliski, California Polytechnic State Univ. (United States)
Anton Clarkson, California Polytechnic State Univ. (United States)
Albert A. Liddicoat, California Polytechnic State Univ. (United States)


Published in SPIE Proceedings Vol. 5559:
Advanced Signal Processing Algorithms, Architectures, and Implementations XIV
Franklin T. Luk, Editor(s)

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