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Proceedings Paper

Automated synthesis of Dadda multipliers
Author(s): Travis Lanier; Jacob Wilcox; Earl E. Swartzlander
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Paper Abstract

Although Dadda multipliers offer the greatest speed potential with a delay proportional to log(n), they are not often used in everyday designs because of their irregular structure and the ensuing difficulty this entails in their implementation. This paper presents a program which automatically generates HDL code describing a Dadda multiplier of specified size. The resulting HDL code is then synthesized to a generic library in the TSMC13G process (0.13um). It is observed that delay increases only marginally when increasing the multiplier size from 16 to 64 bits, while total area increases drastically.

Paper Details

Date Published: 26 October 2004
PDF: 9 pages
Proc. SPIE 5559, Advanced Signal Processing Algorithms, Architectures, and Implementations XIV, (26 October 2004); doi: 10.1117/12.559866
Show Author Affiliations
Travis Lanier, ARM, Ltd. (United States)
Jacob Wilcox, Advanced Micro Devices, Inc. (United States)
Earl E. Swartzlander, Univ. of Texas/Austin (United States)


Published in SPIE Proceedings Vol. 5559:
Advanced Signal Processing Algorithms, Architectures, and Implementations XIV
Franklin T. Luk, Editor(s)

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