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Proceedings Paper

Redundant logarithmic arithmetic for MPEG decoding
Author(s): Mark G. Arnold
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Paper Abstract

Previous research shows the Signed Logarithmic Number System (SLNS) offers lower power consumption than the fixed-point number system for MPEG decoding. SLNS represents a value with the logarithm of its absolute value and a sign bit. Subtraction is harder in SLNS than other operations. This paper examines a variant, Dual-Redundant LNS (DRLNS), where addition and subtraction are equally easy, but DRLNS-by-DRLNS multiplication is not. DRLNS represents a value as the difference of two terms, both of which are represented logarithmically. DRLNS is appropriate for the Inverse Discrete Cosine Transform (IDCT) used in MPEG decoding because a novel accumulator register can contain the sum in DRLNS, but the products are fed to this accumulator in non-redundant SLNS format. Since DRLNS doubles the word size, the accumulator needs to be converted back into SLNS. This paper considers two such methods. One computes the difference of the two parts using LNS. The other converts the two parts separately to fixed point and then computes the logarithm of their difference. A novel factoring of a common term out of the two parts reduces the bus widths. Mitchell's low-cost logarithm/antilogarithm approximation is shown to produce acceptable visual results in this conversion.

Paper Details

Date Published: 26 October 2004
PDF: 11 pages
Proc. SPIE 5559, Advanced Signal Processing Algorithms, Architectures, and Implementations XIV, (26 October 2004); doi: 10.1117/12.559080
Show Author Affiliations
Mark G. Arnold, Lehigh Univ. (United States)

Published in SPIE Proceedings Vol. 5559:
Advanced Signal Processing Algorithms, Architectures, and Implementations XIV
Franklin T. Luk, Editor(s)

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