Share Email Print
cover

Proceedings Paper

FET on ultrathin SOI (fabrication and research)
Author(s): Olga V. Naumova; Irina V. Antonova; Vladimir P. Popov; Yury V. Nastaushev; Tatiana A. Gavrilova; Marina M. Kachanova; Litvin V. Litvin; Alexander L. Aseev
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Some problems arisen from the fabrication of the nano-scale transistors are discussed: modification of the silicon-on-insulator (SOI) under (a) thinning procedure (multiplied oxidation), (b) structuring of the silicon nanolayers. Two types of SOI field effect transistors (FETs) were realized: in-plane-gate FET (IPGFET) with 40 nm minimum channel size and multi-channel top-gate FET on silicon on-insulator. The multi-channel 3D-gate FET fabricated on the uniform doped silicon layers are found to be the most advantageous variant of design.

Paper Details

Date Published: 28 May 2004
PDF: 9 pages
Proc. SPIE 5401, Micro- and Nanoelectronics 2003, (28 May 2004); doi: 10.1117/12.558394
Show Author Affiliations
Olga V. Naumova, Institute of Semiconductor Physics (Russia)
Irina V. Antonova, Institute of Semiconductor Physics (Russia)
Vladimir P. Popov, Institute of Semiconductor Physics (Russia)
Yury V. Nastaushev, Institute of Semiconductor Physics (Russia)
Tatiana A. Gavrilova, Institute of Semiconductor Physics (Russia)
Marina M. Kachanova, Institute of Semiconductor Physics (Russia)
Litvin V. Litvin, Institute of Semiconductor Physics (Russia)
Alexander L. Aseev, Institute of Semiconductor Physics (Russia)


Published in SPIE Proceedings Vol. 5401:
Micro- and Nanoelectronics 2003
Kamil A. Valiev; Alexander A. Orlikovsky, Editor(s)

© SPIE. Terms of Use
Back to Top