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Proceedings Paper

Study of mask corner rounding effects on lithographic patterning for 90-nm technology node and beyond
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Paper Abstract

This paper presented an integrated simulation framework linking our in-house mask writer simulator and the optical lithography simulation engines to include the mask corner rounding effect in lithographic performance evaluations. In the writer simulator, a modified two-dimensional Gaussian function is used as the functional form of the convolution kernel (point spread function). Parameters of the kernel function for different writing machines are automatically extracted from scanning electron microscope (SEM) photographs of simple mask pattern geometries. The convolution results of the kernel and the mask layout form the intensity distribution for pattern definition. The isocontour of the resulting image at the desired level of bias can be regarded as a good approximation of the mask shape obtained from a real mask writer. The writer simulator then saves the contour data as the user-specified format of mask file for subsequent lithography simulations. With the aid of this simulation tool, the impacts of mask corner rounding effects on two-dimensional OPCed pattern for 90-nm and 65-nm node lithography processes are quantitatively evaluated. The results show the line end shortening (LES) is greatly influenced by mask corner rounding effects. The LESs in the 65-nm node process are over twice of those in the 90-nm node process. The resolution capability of a 2-stage 16X mask manufacturing process was also studied in this paper. Simulation results indicate the ArF lithography might be required to make this innovative mask-making technology suitable for 90-nm generation and beyond.

Paper Details

Date Published: 20 August 2004
PDF: 8 pages
Proc. SPIE 5446, Photomask and Next-Generation Lithography Mask Technology XI, (20 August 2004); doi: 10.1117/12.557745
Show Author Affiliations
Shuo-Yen Chou, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Jaw-Jung Shin, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
King-Chang Shu, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Jan-Wen You, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Lin-Hung Shiu, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Bin-Chang Chang, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Tsai-Sheng Gau, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Burn J. Lin, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)


Published in SPIE Proceedings Vol. 5446:
Photomask and Next-Generation Lithography Mask Technology XI
Hiroyoshi Tanabe, Editor(s)

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