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Proceedings Paper

Low-frequency noise in SiGeC-based pMOSFETs
Author(s): M. Jamal Deen; Ognian Marinov; David Onsongo; Sanjay Banerjee
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Paper Abstract

The SiGeC ternary alloy seems to be an attractive material system for Si-based device applications, because the incorporation of a small amount of C in the high-mobility SiGe layer offers an additional degree of freedom for tuning the bandgap, band offsets and the lattice strain in group IV heterostructures. In this work, detailed low-frequency noise (LFN) results in SiGeC pMOSFETs are presented. Our experimental results in saturation regime of the SiGe MOSFET show that the noise in SiGeC MOSFETs at gate bias |VGS-VT|<0.4V can be referred to the gate terminal as a noise voltage SVG=VG2, which implies (ΔN) fluctuation with correlated noise in the cap and SiGeC channel currents. Overall, the trend shows that the gate referred noise voltage scales inversely with the gate area, and that the variation of the noise level has log-normal distribution. Therefore, the noise in SiGeC MOSFETs can be expressed as S=Savg*exp(t*σNp), where t=±1,...,±3 is a coefficient selected for desired confidence probability of 0.6,...,0.99 respectively, and σ is the standard deviation of the log-normal distribution of the noise level around its average Savg, later given by (ΔN-Δμ) fluctuation in the cap layer and SiGeC channel of pMOSFET.

Paper Details

Date Published: 25 May 2004
PDF: 11 pages
Proc. SPIE 5470, Noise in Devices and Circuits II, (25 May 2004); doi: 10.1117/12.548006
Show Author Affiliations
M. Jamal Deen, McMaster Univ. (Canada)
Ognian Marinov, McMaster Univ. (Canada)
David Onsongo, Univ. of Texas/Austin (United States)
Sanjay Banerjee, Univ. of Texas/Austin (United States)

Published in SPIE Proceedings Vol. 5470:
Noise in Devices and Circuits II
Francois Danneville; Fabrizio Bonani; M. Jamal Deen; Michael E. Levinshtein, Editor(s)

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