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Proceedings Paper

Noise modeling and performance in 0.15-μm fully depleted SOI MOSFET
Author(s): Guillaume Pailloncy; Benjamin Iniguez; Gilles Dambrine; Morin Dehan; Jean-Pierre Raskin; Hideaki Matsuhashi; Pierre Delatte; Francois Danneville
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Paper Abstract

This paper is intended to describe on one part theoretical results issued from a physical noise modeling and on the other part the noise performance of Fully Depleted (FD) SOI MOSFET of 0.15 μm gate length. In the theoretical part, the physical noise model is applied to two distinct applications; first to study the influence of the microscopic diffusion noise sources definition (located in the channel device) on the noise performance, second to check the concept of un-correlated noise sources, if one uses an input noise voltage and output drain noise current representation. In the experimental part, both bias and frequency dependences of the measured noise performances of the 0.15 μm gate length fully depleted (FD) SOI MOSFET (OKI technology) are presented, and a comparison with the results issued from the physical noise model is proposed.

Paper Details

Date Published: 25 May 2004
PDF: 9 pages
Proc. SPIE 5470, Noise in Devices and Circuits II, (25 May 2004); doi: 10.1117/12.546669
Show Author Affiliations
Guillaume Pailloncy, Institut d'Electronique de Microélectronique et de Nanotechnologie (France)
Benjamin Iniguez, Univ. Rovira i Virgili (Spain)
Gilles Dambrine, Institut d'Electronique de Microélectronique et de Nanotechnologie (France)
Morin Dehan, Univ. Catholique de Louvain (Belgium)
Jean-Pierre Raskin, Univ. Catholique de Louvain (Belgium)
Hideaki Matsuhashi, Oki Electric Industry Co., Ltd. (Japan)
Pierre Delatte, CISSOID (Belgium)
Francois Danneville, Institut d'Electronique de Microélectronique et de Nanotechnologie (France)


Published in SPIE Proceedings Vol. 5470:
Noise in Devices and Circuits II
Francois Danneville; Fabrizio Bonani; M. Jamal Deen; Michael E. Levinshtein, Editor(s)

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