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Proceedings Paper

Improvement of aluminum interconnect overlay measurement capability through metrology and hardmask process development
Author(s): Albert L. Ihochi; Matthew E. Ross
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Paper Abstract

Overlay measurement of metal interconnect layers that exhibit contrast variation has historically been problematic. The appearance of random grain structure surrounding the overlay target obscures the edge contrast, leading to significant noise in measurement and residual error of fit. Large residuals reduce confidence in modeled scanner correctable terms, increasing the likelihood of false scanner corrections which can lead to poor process control. We have developed a new measurement methodology that minimizes the effect of grain-induced noise for overlay metrology. Measurements which utilize the new parameters have shown a 30% reduction in mean-square (MS) residual error and a 39% reduction in variance. In addition, predicted wafer maximum overlay error has decreased by 14%, with a 16% improvement in wafer-to-wafer variance. This type of performance improvement is expected to have a significant impact on rework reduction. The primary source of visible grain structure in the aluminum interconnect layer has been attributed to the metal hardmask deposition process. By moving to a lower temperature hardmask deposition, the grain has been significantly reduced. This has resulted in a 15% further reduction of MS residual error.

Paper Details

Date Published: 24 May 2004
PDF: 12 pages
Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); doi: 10.1117/12.544229
Show Author Affiliations
Albert L. Ihochi, Intel Corp. (United States)
Matthew E. Ross, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 5375:
Metrology, Inspection, and Process Control for Microlithography XVIII
Richard M. Silver, Editor(s)

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