Share Email Print
cover

Proceedings Paper

Evaluation of new in-chip and arrayed line overlay target designs
Author(s): Ravikiran Attota; Richard M. Silver; Michael Bishop; Egon Marx; Jau-Shi Jay Jun; Michael Stocker; Mark P. Davidson; Robert D. Larrabee
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Two types of overlay targets have been designed and evaluated for the study of optical overlay metrology. They are in-chip and arrayed overlay targets. In-chip targets are three-bar two-level targets designed to be placed in or near the active device area of a chip. They occupy a small area in the range of 5 μm2 to 15 μm2 and have line widths, which are nominally device dimensions. The close proximity of the line features result in strong proximity effects. We have used two well-established theoretical models to simulate and study the effects of proximity on overlay measurements. In this paper, we also present a comparison of optical overlay results with scanning electron microscope measurements. Arrayed targets have also been designed to improve and enhance the optical signal for small critical dimension features. We have also compared theoretical simulations of arrayed targets to experimental results. In these comparisons we observe a significant variation in the location of the best focus image with respect to the features. The through-focus focus-metric we have implemented in the current work to determine the best focus image shows interesting properties with potential applications for line width metrology and process control. Based on simulation results, the focus-metric is sensitive to changes in line width dimensions on the nanometer scale.

Paper Details

Date Published: 24 May 2004
PDF: 8 pages
Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); doi: 10.1117/12.539164
Show Author Affiliations
Ravikiran Attota, National Institute of Standards and Technology (United States)
Richard M. Silver, National Institute of Standards and Technology (United States)
Michael Bishop, International SEMATECH (United States)
Egon Marx, National Institute of Standards and Technology (United States)
Jau-Shi Jay Jun, National Institute of Standards and Technology (United States)
Michael Stocker, National Institute of Standards and Technology (United States)
Mark P. Davidson, Spectel Company (United States)
Robert D. Larrabee, National Institute of Standards and Technology (United States)


Published in SPIE Proceedings Vol. 5375:
Metrology, Inspection, and Process Control for Microlithography XVIII
Richard M. Silver, Editor(s)

© SPIE. Terms of Use
Back to Top