Share Email Print
cover

Proceedings Paper

An efficient parallel architecture for MPEG-4 zerotree encoder
Author(s): Chao Xu; Qing-Yun Shi
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

This paper presents a novel parallel hardware architecture for MPEG-4 zerotree encoder. Under the architecture, a parallel processing of multi bit-planes is fulfilled through a preprocess until and multi-encoding units. The preprocess unit consists of mainly a bit-not-and and a bit-or logic circuits. It ensures sufficiently that efficient encoding in each bit-plane is performed independently. Each encoding until uses a fast technique to assign symbols by taking advantage of MPEG-4 zerotree coding symbol alphabet, and to select valid data to output using a ZTR address buffer.

Paper Details

Date Published: 25 September 2003
PDF: 5 pages
Proc. SPIE 5286, Third International Symposium on Multispectral Image Processing and Pattern Recognition, (25 September 2003); doi: 10.1117/12.539061
Show Author Affiliations
Chao Xu, Peking Univ. (China)
Qing-Yun Shi, Peking Univ. (China)


Published in SPIE Proceedings Vol. 5286:
Third International Symposium on Multispectral Image Processing and Pattern Recognition
Hanqing Lu; Tianxu Zhang, Editor(s)

© SPIE. Terms of Use
Back to Top