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Proceedings Paper

A VLSI architecture for lifting-based wavelet transform with power efficient
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Paper Abstract

In this paper, an efficient VLSI architecture for biorthogonal 9/7 wavelet transform by lifting scheme is presented. The proposed architecture has many advantages including, symmetrical forward and inverse wavelet transform as a result of adopting pipeline parallel technique, as well as area and power efficient because of the decrease in the amount of memory required together with the reduction in the number of read/write accesses on account of using embedded boundary data-extension technique. We have developed a behavioral Verilog HDL model of the proposed architecture, which simulation results match exactly that of the Matlab code simulations. The design has been synthesized into XILINX xcv50e-cs144-8, and the estimated frequency is 100MHz.

Paper Details

Date Published: 25 September 2003
PDF: 5 pages
Proc. SPIE 5286, Third International Symposium on Multispectral Image Processing and Pattern Recognition, (25 September 2003); doi: 10.1117/12.538858
Show Author Affiliations
Chengyi Xiong, Huazhong Univ. of Science and Technology (China)
Sheng Zheng, Huazhong Univ. of Science and Technology (China)
Jinwen Tian, Huazhong Univ. of Science and Technology (China)
Jian Liu, Huazhong Univ. of Science and Technology (China)


Published in SPIE Proceedings Vol. 5286:
Third International Symposium on Multispectral Image Processing and Pattern Recognition
Hanqing Lu; Tianxu Zhang, Editor(s)

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