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Proceedings Paper

Process latitude measurements and their implications for CD control in EUV lithography
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Paper Abstract

We have exposed 10 wafers on the Engineering Test Stand (ETS), the 0.1 NA EUV scanner at Sandia National Laboratories in Livermore, CA. The EUV reflective mask was fabricated in-house using a Ta-based absorber stack on Mo/Si multilayers. The printed wafers contained different line sizes and pitches, line-end shortening measurement structures, contact holes, and patterns for estimating absorber defect printability. The depths of focus of each feature are typically 2 um due to the small NA of the scanner, and these should decrease by at least a factor of 6.25 as the NA's increase to 0.25. The data from measurements of line size through pitch and line-end shortening test structures indicate that both 1D and 2D optical proximity correction will be required. Defects that are either notches in or protrusions from absorber lines are the first to print, and they begin to print when they reach approximately 15~nm (1X) in size. This size threshold is in accordance with the 2003 ITRS specifications. We also report the first printing of SRAM bitcells with EUV lithography.

Paper Details

Date Published: 20 May 2004
PDF: 10 pages
Proc. SPIE 5374, Emerging Lithographic Technologies VIII, (20 May 2004); doi: 10.1117/12.537366
Show Author Affiliations
Jonathan Cobb, Motorola, Inc. (United States)
Richard Peters, Motorola, Inc. (United States)
Sergei Postnikov, Motorola, Inc. (United States)
Scott D. Hector, Motorola, Inc. (United States)
Bing Lu, Motorola, Inc. (United States)
Eric Weisbrod, Motorola, Inc. (United States)
James R. Wasson, Motorola, Inc. (United States)
Pawitter Mangat, Motorola, Inc. (United States)
Donna O'Connell, Sandia National Labs. (United States)


Published in SPIE Proceedings Vol. 5374:
Emerging Lithographic Technologies VIII
R. Scott Mackay, Editor(s)

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