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Proceedings Paper

Yield loss in lithographic patterning at the 65nm node and beyond
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Paper Abstract

Parametric yield loss is an increasing fraction of total yield loss. Much of this originates in lithography in the form of pattern-limited yield. In particular, the ITRS has identified CD control at the 65nm technology node as a potential roadblock with no known solutions. At 65nm, shrinking design rules and narrowing process windows will become serious yield limiters. In high-volume production, corrections based on lot averages will have diminished correlation to device yield because APC systems will dramatically reduce error at the lot and wafer levels. As a result, cross-wafer and cross-field errors will dominate the systematic variation on 300mm wafers. Much of the yield loss will arise from hidden systematic variation, including intra-wafer dose and focus errors that occur during lithographic exposure. In addition, corollary systematic variation in the profiles of critical high-aspect-ratio structures will drive requirements for vertical process control. In this work, we model some of the potential yield losses and show how sensitive focus-exposure monitors and spectroscopic ellipsometry can be used to reduce the impact of hidden error on pattern limited yield, adding tens of millions of dollars in additional revenue per factory per year.

Paper Details

Date Published: 29 April 2004
PDF: 11 pages
Proc. SPIE 5378, Data Analysis and Modeling for Process Control, (29 April 2004); doi: 10.1117/12.537349
Show Author Affiliations
Kevin M. Monahan, KLA-Tencor Corp. (United States)
Brad Eichelberger, KLA-Tencor Corp. (United States)
Matt Hankinson, KLA-Tencor Corp. (United States)
John Robinson, KLA-Tencor Corp. (United States)
Mike Slessor, KLA-Tencor Corp. (United States)


Published in SPIE Proceedings Vol. 5378:
Data Analysis and Modeling for Process Control
Kenneth W. Tobin, Editor(s)

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