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Proceedings Paper

Double exposure to reduce overall line-width variation of 80-nm DRAM gate
Author(s): Won Kwang Ma; Chang-Moon Lim; Se Young Oh; Byung Ho Nam; Seung Chan Moon; Ki Soo Shin
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Paper Abstract

As design rule shrinks down continuously, various technology have been developed to extend the resolution limits of lithography. One of those is Double Exposure Technology(DET). This paper is about not only resolution improvement but also Critical Dimension(CD) variation reduction with DET. As the design rule shrinks below 100nm, the core/peripheral area where we used to think we had sufficient margin is becoming the bottle neck for device fabrication. In this paper, in order to compare optimized single exposure (cell focus) and DET (cell, core/peripheral focus) for critical dimension uniformity(CDU) on cell and core/peripheral area, CDU was measured from wafer by use of simulation and measurement. Gate layer of DRAM device was used for the experiment. Exposure condition for the single exposure was set to crosspole and for DET, dipole and conventional respectively. Optical proximity correction(OPC) was done with in-house simulation tool on stiching area of the double exposure experiment. Same exposure tool and same process condition were used for each experiment and only the exposure condition was changed to compare local CDU, intra-field CDU, wafer CDU to find out how much CD variation can be reduced.

Paper Details

Date Published: 28 May 2004
PDF: 8 pages
Proc. SPIE 5377, Optical Microlithography XVII, (28 May 2004); doi: 10.1117/12.536358
Show Author Affiliations
Won Kwang Ma, Hynix Semiconductor Inc. (South Korea)
Chang-Moon Lim, Hynix Semiconductor Inc. (South Korea)
Se Young Oh, Hynix Semiconductor Inc. (South Korea)
Byung Ho Nam, Hynix Semiconductor Inc. (South Korea)
Seung Chan Moon, Hynix Semiconductor Inc. (South Korea)
Ki Soo Shin, Hynix Semiconductor Inc. (South Korea)


Published in SPIE Proceedings Vol. 5377:
Optical Microlithography XVII
Bruce W. Smith, Editor(s)

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