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Proceedings Paper

Way for LEEPL technology to succeed in memory device application
Author(s): In-Sung Kim; Sang-Gyun Woo; Han-Ku Cho; Woo-Sung Han; Joo-Tae Moon
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Paper Abstract

Lithography for 65nm-node device is drawing a lot of attentions these days especially because lithography solution for this node is not clear and even tool makers tend to wait for the consensus in lithography roadmap to avoid the risk of erroneous amount of investment. Recently proposed concept of low energy electron-beam proximity-projection lithography (LEEPL)1,2 technology has already released its first production machine in 2003, which is being expected to cover the design rule down to 65nm-node and even smaller3. Although production of semiconductor device has been pursuing optical lithography, without any optical technology that is proved as a convincing solution for 65nm node and below, we need to take account of all the candidates. So we made an investigation on LEEPL technology and evaluated beta and first production tool to see the feasibility of printing sub-70nm resolution and of optic-first mix-and-match overlay from a chip maker’s point of view. Two different kinds of stencil masks were fabricated for the evaluation, which are fabricated in SiC and Si membrane. The former mask is for sparse contact holes(C/H) and the latter for dense C/Hs. Beta-tool showed a good resolving power of sub-70nm sparse C/Hs of SRAM with negligibly small proximity effect. It implies that LEEPL does not require much effort for proximity correction comparing to that required in optical lithography, which is one of the biggest issues in low-k1. LEEPL also showed a good capability of optic-first mix-and-match overlay correction and this is the most stringent and important functionality for optic-first mix-and-match application. However random intra-membrane image placement(IP) error that is a little bit larger than the requirement for sub-70nm node was observed, which is interpreted to come from the larger stress of 100MPa in 3X3mm2 dry-etched SiC unit membrane. For dense C/Hs, we failed, to the contrary, to obtain any good quality of stencil masks for DRAM cell patterns because of e-beam proximity effect which is unavoidable in the reversed order of front-side forward direct writing and back-side later membrane formation. Pros and cons of LEEPL technology are discussed based on the evaluation results and estimation from the memory device standpoint. We also propose a novel concept of stencil mask that can be helpful in memory device application.

Paper Details

Date Published: 20 May 2004
PDF: 8 pages
Proc. SPIE 5374, Emerging Lithographic Technologies VIII, (20 May 2004); doi: 10.1117/12.536253
Show Author Affiliations
In-Sung Kim, Samsung Electronics Co., Ltd. (South Korea)
Sang-Gyun Woo, Samsung Electronics Co., Ltd. (South Korea)
Han-Ku Cho, Samsung Electronics Co., Ltd. (South Korea)
Woo-Sung Han, Samsung Electronics Co., Ltd. (South Korea)
Joo-Tae Moon, Samsung Electronics Co., Ltd. (South Korea)


Published in SPIE Proceedings Vol. 5374:
Emerging Lithographic Technologies VIII
R. Scott Mackay, Editor(s)

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